
// Library name: VLSI_PROJECT
// Cell name: amk_inverter
// View name: schematic
subckt amk_inverter VDD VSS in out
    T1 (out in VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (out in VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 nrs=1.5652 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_inverter
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_buf
// View name: schematic
subckt amk_buf VDD VSS bout in
    I1 (VDD VSS net10 bout) amk_inverter
    I0 (VDD VSS in net10) amk_inverter
ends amk_buf
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: nmos_amp
// View name: schematic
subckt nmos_amp VDD VSS out ref vin\+ vin\-
    T4 (VDD net10 net10 VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (out net10 VDD VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (VSS ref net057 VSS) lpnfet l=15.0u w=240.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.32e-13 as=1.32e-13 pd=1.58u ps=1.58u nrd=0.9167 nrs=0.9167 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T1 (net10 vin\+ net057 VSS) lpnfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T7 (net057 vin\- out VSS) lpnfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends nmos_amp
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: pmos_amp
// View name: schematic
subckt pmos_amp VDD VSS out ref vin\+ vin\-
    T1 (VSS net5 net5 VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T7 (out net5 VSS VSS) lpnfet l=10u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (net036 ref VDD VDD) lppfet l=10u w=200n nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-13 as=1.1e-13 pd=1.5u ps=1.5u nrd=1.1 nrs=1.1 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T4 (net5 vin\+ net036 VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T5 (net036 vin\- out VDD) lppfet l=5u w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.22 nrs=0.22 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends pmos_amp
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: comparator1
// View name: schematic
I8 (VDD VSS net043 net41) amk_buf
I9 (VDD VSS net039 net31) amk_buf
I7 (VDD VSS amp1o net078) amk_buf
I10 (VDD VSS out net15) amk_buf
T2 (net039 net22 net15 VDD) lppfet l=1u w=20u nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-11 as=1.1e-11 pd=41.1u ps=41.1u nrd=0.011 nrs=0.011 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
T1 (net043 amp1o net15 VDD) lppfet l=1u w=20u nf=1 m=1 par=1 ngcon=1 \
        ad=1.1e-11 as=1.1e-11 pd=41.1u ps=41.1u nrd=0.011 nrs=0.011 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
T3 (net039 amp1o net15 VSS) lpnfet l=1u w=10u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-12 as=5.5e-12 pd=21.1u ps=21.1u nrd=0.022 nrs=0.022 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
T0 (net043 net22 net15 VSS) lpnfet l=1u w=10u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-12 as=5.5e-12 pd=21.1u ps=21.1u nrd=0.022 nrs=0.022 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
I6 (VDD VSS amp1o net22) amk_inverter
I2 (VDD VSS net31 vref in\+ in\-) nmos_amp
I1 (VDD VSS net41 vref in\+ in\-) pmos_amp
I0 (VDD VSS net078 vref in\+ in\-) pmos_amp
